1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a semiconductor device which is required to operate with a low voltage as well as a method of manufacturing the same.
2. Description of the Background Art
Transistors selectively attains on and off states, and a current that flows between a source and a drain in the on state, i.e., when a voltage is placed on the gate electrode will now be referred to as an “on current”. The magnitude of the on current is proportional to a quantity Q of electric charges induced in a channel region formed at a semiconductor substrate. This charge quantity Q is expressed as follows in connection with an effective film thickness EOT of a gate insulating film.Q∝Cinv×(Vg−Vt)where Vg represents a voltage between the gate electrode and the semiconductor substrate, Vt represents a threshold voltage and Cinv is proportional to (1/(EOT+ΔT). ΔT is a capacitance occurring between the gate electrode and the semiconductor substrate except for the gate insulating film. Therefore, the above relationship can also be expressed as follows:Q∝(Vg−Vt)/(EOT+ΔT)
It can be understood that the on current can be increased by increasing charge quantity Q, which can be increased by reducing (EOT+ΔT). According to the current technology, the EOT is already equal to 2.0 nm or less, and it is expected that an EOT of a High-K gate insulating film of which practical use is being studied will be practically reduced to about 1.0 nm. However, further reduction of the thickness is difficult. Meanwhile, it has been requested to put the metal gate electrode to practical use as a method of reducing ΔT. The “metal gate electrode” is a gate electrode made of metal or metallic compound having electrical conductivity. The metal gate electrode may be simply referred to as a “metal gate”. The metal gate electrode does not cause depletion in contrast to the gate electrode made of polycrystalline silicon, and therefore allows reduction of ΔT to 0.4 nm which is an ultimate value achieved by quantization effect.
For example, “Process Integration, Devices, and Structures”, page 12, table 47b in “2003 Edition of ITRS” (International Technology Roadmap for Semiconductors) (http://public.itrs.net/Files/2003ITRS/Home2003.htm) has described a forecast of specifications that will be requested in logic elements from 2010 to 2018. For 45 nm node and later in this table, it is required to put the metal gate electrode to the practical use.
A large obstacle to the practical use of the metal gate electrode is that control of the threshold voltage is difficult. For example, a CMOS (Complementary Metal-Oxide Semiconductor) structure is a combination of n- and p-type transistors, and an n-type MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) requires a gate electrode of a small work function. Also, a p-type MISFET requires a gate electrode of a large work function. In the conventional gate electrodes made of polycrystalline silicon, the work functions of the gate electrodes can be easily adjusted corresponding to the n- and p-type MISFETs by using the ion implantation method, respectively. The polycrystalline silicon heavily doped with, e.g., phosphorus as n-type impurities exhibits the work function of about 4.0 eV. The polycrystalline silicon heavily doped with, e.g., boron as p-type impurities exhibits the work function of about 5.2 eV. By using the n-type polycrystalline silicon and p-type polycrystalline silicon for the n- and p-type MISFETs as described above, respectively, the work functions similar to that of the substrate channel can be easily achieved. In this manner, both the n- and p-types of MISFETs can be configured to have small threshold voltages so that the CMOS structure that can operate with a low voltage can be achieved.
In contrast to the above, the work function of the metal gate electrode takes a value unique to an electrode material, and cannot be adjusted easily in contrast to the polycrystalline silicon. Therefore, it is necessary to provide materials suitable for the electrodes of the n- and p-type MISFETs at respective regions. Thus, two kinds of materials must be arranged at different plane regions on the same chip, respectively. This complicates the process of forming them. The above structure requires, e.g., such steps that a layer of a first material is formed on a gate insulating film, and then a layer of a second material is formed after removing a first metal material from a partial region in the first material layer. This manufacturing method suffers from a problem that deterioration of the gate insulating film cannot be avoided.
For overcoming the above problem, Japanese Patent Laying-Open No. 2001-203276 has proposed a method in which titanium nitride (TiN) is used in a gate electrode, and a work function is changed by changing a concentration or content of nitrogen in the titanium nitride. This method allows employment of the ion implantation method which is similar to that used in the conventional manufacturing method predicted on the gate electrode of polycrystalline silicon, and therefore the implantation dose of nitride in each of regions of the n- and p-type MISFETs can be changed to form the gate electrode having two kinds of work functions in each region.
Meanwhile, the fact that heat treatment causes large changes in work function of the titanium nitride is disclosed by M. S. Joo et al., “Behavior of Effective Work Function in Metal/High-K Gate Stack under High Temperature Process”, Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials, p. 202.